1. Field of the Invention
The present invention relates to a semiconductor device.
Priority is claimed on Japanese Patent Application No. 2010-123254, filed May 28, 2010, the content of which is incorporated herein by reference.
2. Description of the Related Art
Generally, a semiconductor device, such as a DRAM (Dynamic Random Access Memory), includes multiple memory cells each including a storage capacitor and a transistor which are coupled in series. As such a semiconductor device, Japanese Patent Laid-Open Publication No. 2002-134506 discloses a structure in which a plate voltage VPLT is equally supplied to a plate electrode that is one electrode of a storage capacitor in each memory cell.
In such a case, a transistor is coupled between a storage electrode that is the other electrode of the storage capacitor and a corresponding bit line. A gate electrode of the transistor is coupled to a word line. A plate voltage VPLT is generally set to be ½ VARY where VARY is an operational power voltage of the memory cell array.
Data 1 is defined as a state in which the storage electrode of the storage capacitor is charged to a voltage higher than the VARY (generally to VPERI that is an operational voltage of a peripheral circuit). In other words, Data 1 is defined as a state in which electric charge, the voltage value of which is greater than ½ VARY supplied to the plate electrode, is stored in the storage electrode in the positive direction.
Data 0 is defined as a state in which the storage electrode of the storage capacitor is charged to a ground voltage VSS. In other words, Data 0 is defined as a state in which electric charge, the voltage of which is ½ VARY supplied to the plate electrode, is stored in the storage electrode in the negative direction.
When reading of data from each memory cell, a predetermined memory cell is selected while the bit line is pre-charged to ½ VARY. In this case, when the selected memory cell stores Data 1, a voltage of the storage electrode of the storage capacitor in the selected memory cell decreases since the electric charge is transferred to the bit line. When the selected memory cell stores Date 0, on the other hand, the voltage of the storage electrode increases since the electric charge is introduced from the bit line. In contrast, a voltage of the bit line increases when the memory cell stores Data 1, and decreases when the memory cell stores Data 0. The variation in voltage of the bit line is amplified by a sense amplifier to determine whether the stored data is Data 1 or Data 0.
Regarding semiconductor devices, such as a recent DRAM, demand for higher memory capacity has been increasing, which has caused miniaturization of DRAM. Consequently, parasitic capacitance of storage electrode has been much decreased compared to that of the conventional storage electrode.
The inventor of the present invention found that a variation in voltage of the storage electrode of the storage capacitor upon reading of data is detected as a variation in voltage of the plate electrode. In other words, if the parasitic capacitance is large, the charged voltage of the parasitic capacitance is supplied to the plate electrode. Thereby, a variation in the voltage of the storage electrode has little effect on a voltage of the plate electrode. However, as the parasitic capacitance has been made small, a variation in the voltage of the storage electrode has a direct effect on a variation in the voltage of the plate electrode.
Consequently, the variation in the voltage of the plate electrode has great effect on the voltage of the storage electrode of another storage capacitor, thereby occasionally causing malfunction of the sense amplifier through the bit line.